The present disclosure relates to semiconductor integrated circuits and, more particularly, to a semiconductor integrated circuit (IC) capable of reducing leakage currents.
Upon approaching microscopic processing levels with the dimensions of tens of nanometers in semiconductor IC fabrication technology, semiconductor IC devices meet with leakage currents that are increasing exponentially. It therefore becomes important to reduce leakage currents in mobile apparatuses that are supplied with power from batteries.
There have been various techniques for reducing leakage currents and, thus, leakage power. Among those techniques, that of power gating, developed in recent years, is efficient for reducing leakage currents in a standby state. In the power gating technique, sleep transistors are used as switches for interrupting the power supply to circuit blocks conditioned in the standby state. Thus, it is possible to effectively reduce a rate of leakage power. Nevertheless, it is inevitable to supply power once again to a block that needs to be activated. During this process, an abrupt variation of current is induced so as to result in inadvertent noise. Such noise is called ground bounce noise, adversely affecting circuits and inducing malfunctions.
To reduce such ground bounce noise, a general power gating circuit operates by turning on sleep transistors in sequence with respective time delays. Because the sleep transistors are sequentially turned on, abrupt current variations do not occur. In order to provide, for sufficient delay, however, a chip size becomes much larger because of the many delay units that are required.
Additionally, there is a way of blocking an abrupt variation of current by connecting two sleep transistors in series and connecting a capacitor between the sleep transistors, but this may degrade chip performance because of a voltage drop due to the sleep transistors.
Therefore, a power gating circuit advantageous to chip size and functions, minimizing ground bounce noises, is needed.